| 000 | 01408nam a2200277 a 4500 | ||
|---|---|---|---|
| 001 | 000013533 | ||
| 005 | 20160221095243.0 | ||
| 008 | 101209s2008 xxuade frn 001 0 eng d | ||
| 942 | _c | ||
| 020 | _a0132365049 (pasta dura) | ||
| 020 | _a9780132365048 (pasta dura) | ||
| 040 | _aCO-BrUAC | ||
| 041 | 0 | _aeng. | |
| 082 | 0 | 0 |
_a621.3815 _bE23 _222 ed. |
| 100 | 1 | _aEdlund, Greg. | |
| 245 | 1 | 0 |
_aTiming analysis and simulation for signal integrity engineers / _cGreg Edlund. |
| 260 |
_aNew Jersey : _bPrentice Hall, _c2008. |
||
| 300 |
_a241 p. : _bil., grafs., fot. byn., tbls., planos, etc. |
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| 490 | 0 | _aPrentice Hall modern semiconductor design series | |
| 504 | _aIncluye referencia bibliográficas, índice, etc. | ||
| 544 | 1 | _aDisponible en la Colección General. | |
| 505 | 0 |
_gPreface -- _gAcknowledgments -- _gAbout the author -- _gAbout the cover -- _gCap. _g1. _tEngineering reliable digital interfaces -- _g2. _tChip-to-chip timing -- _g3. _tInside IO circuits -- _g4. _tModeling 3D discontinuities -- _g5. _tPractical 3D examples -- _g6. _tDDR2 case study -- _g7. _tPCI express case study -- _gA. _tA short CMOS and SPICE primer -- _gB. _tA Stroll througj 3D fields -- _tEndnotes -- _gIndex. |
|
| 650 | 1 | 4 |
_aElectronica Digital _xDiseño y Construcción |
| 650 | 1 | 4 |
_aProceso de Señales _xTécnicas Digitales |
| 830 | 0 |
_aPrentice Hall modern semiconductor design series _pPrentice Hall Signal Integrity Library |
|
| 999 |
_c13458 _d13458 |
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