TY  - BOOK
AU  - Edlund,Greg
TI  - Timing analysis and simulation for signal integrity engineers
T2  - Prentice Hall modern semiconductor design series
SN  - 0132365049 (pasta dura)
U1  - 621.3815 22 ed.
PY  - 2008///
CY  - New Jersey
PB  - Prentice Hall
KW  - Electronica Digital
KW  - Diseño y Construcción
KW  - Proceso de Señales
KW  - Técnicas Digitales
N1  - Incluye referencia bibliográficas, índice, etc; Preface --; Acknowledgments --; About the author --; About the cover --; Cap; 1; Engineering reliable digital interfaces --; 2; Chip-to-chip timing --; 3; Inside IO circuits --; 4; Modeling 3D discontinuities --; 5; Practical 3D examples --; 6; DDR2 case study --; 7; PCI express case study --; A; A short CMOS and SPICE primer --; B; A Stroll througj 3D fields --; Endnotes --; Index
ER  -